1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device used as a main memory or a local memory in a system where a wide bandwidth is required.
2. Description of the Background Art
There has been remarkable evolution in the speed of computer systems. Now, efforts are made to increase the speed corresponding to DRAMs (Dynamic Random Access Memory) functioning as the main memory. With the ever increasing data rate required in accordance with a higher speed system such as a MPU (Micro Processing Unit), the trend is to further increase the speed.
As the technique to increase the speed of a DRAM, various approaches have been proposed such as increasing the operating frequency of the external data bus through which data is input or output to or from a DRAM, and providing particular data transmission methods oriented to the timing of both edges of the clock. In practice, various problems are encountered such as an insufficient valid period of data caused by higher frequencies to prevent proper data input/output, occurrence of noise, and increase in power consumption.
Attention is focused on the technology of improving the usage efficiency of the external data bus as one way to improve the bandwidth of the main memory effectively without physical difficulty.
FIG. 21 is a timing chart for describing the data input/output timing during the read/write operation in a conventional DRAM.
It is assumed that the DRAM of interest has the write latency set to 1, the CAS latency set to 2, and the burst length set to 4.
At time t1, a write command is input. At the elapse of one clock cycle at time t2, four data K, L, M and M equal to the burst length are transmitted to an external data bus (also simply referred to as xe2x80x9cdata busxe2x80x9d hereinafter) via an input terminal at each activation timing of a clock signal CLK.
At time t3 corresponding to the elapse of two clock cycles from time t1 when a write command has been generated, data K, L, M and N are sequentially written into a memory cell array.
In the case where a new write command is generated at time t4 when the last write data N of the first write command is transmitted to the data bus, data k, l, m and n can be transmitted to the data bus from time t5. A write operation to the memory cell array can be carried out under the set CAS latency.
In other words, when a write command is designated continuously, the so-called gap corresponding to an idle state of the data bus between commands will not be generated.
Consider the case where a read command is designated at time t7. In a readout operation, the designated data must be read out from the memory cell array to be transmitted to the data bus. Therefore, the readout operation cannot be initiated during the writing operation in which the designated write data is written into the memory cell array before time t7. This means that data E is read out from the memory cell only after 1 clock cycle from the designation of the read command. Data E is output to the data bus at time t8 corresponding to 2 clock cycles from time t7. From time t8, four read data E, F, G and H equal to the burst length are transmitted to the data bus.
When a second read command is continuously designated at time t9, data e corresponding to the second read command can be read out at the clock timing immediately succeeding the readout of data H from the memory cell array corresponding to the first read command. At time t10, data e can be transmitted with no gap right after the output of read data H.
As described with reference to FIG. 21, the data bus can be used with no gaps to achieve high usage efficiency of the data bus when only read operations or only write operations are continued in the conventional DRAM. However, when a combination of a read operation and a write operation is continuously designated, it will become difficult to maintain a high usage efficiency of the data bus since a gap period represented by tg in FIG. 21 is generated.
The cause of such a problem when a read operation and a write operation are designated continuously is set forth in the following. The first factor is that the data base through which data is transferred with respect to the DRAM is provided in common for both operations despite the fact that the data transfer direction differs between the read operation and the write operation. The second factor is that it is extremely difficult to freely execute a read operation and a write operation at the same time in the memory cell array of a DRAM.
An object of the present invention is to provide a structure of a highspeed semiconductor memory device having a wide bandwidth by avoiding concurrence of a read operation and a write operation in a data bus and a memory cell array to improve the data bus usage efficiency.
According to an aspect of the present invention, a semiconductor memory device that can input/output a plurality of data transmitted as a data train in time series by an external data bus in each one readout operation and one write operation includes a memory cell array, a control circuit, a row select circuit and column select circuit, a write data retain circuit, a read data retain circuit, and an input/output select circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix.
The control circuit generates a command signal to carry out a read operation and a write operation of data with respect to a memory cell array.
The row select circuit and the column select circuit select a plurality of select memory cells that become the subject of one read operation and one write operation.
The write data retain circuit temporarily holds a plurality of data transmitted through the external data bus, and then transmits the same to the memory cell array in a write operation.
The read data retain circuit temporarily holds a plurality of data output from the memory cell array, and then sequentially transmits the data to the external data bus in a readout operation.
The input/output select circuit transfers data between each of a plurality of select memory cells and the write and read data retain circuits.
The main advantage of the present invention is that data of a wide bandwidth can be processed speedily by improving the usage efficiency of the data bus and avoiding concurrence of a read operation and a write operation in the memory cell array, since the transfer of the data between the memory cell array and the data bus is carried out independently by the read data retain circuit used in a read operation and the write data retain circuit used in the write operation.